1. Field of the Invention
The present invention generally relates to systems for designing circuits and, more particularly, to systems for modelling and synthesizing circuits such as gate array or cell-based application specific integrated circuits (ASICs) using graphical representations.
2. State of the Art
It is known to describe or specify circuit layouts during their design using schematic symbols (e.g., logic gate symbols) and wire connections. These schematic representations enable designers to view layouts as a whole, including connections between electrical components in the layouts.
Logic synthesis tools also have been developed for assisting in the transition from a schematic circuit representation to a set of logical equations, such as Boolean equations. The logical equations define circuit operations and can be used to construct efficient implementations of circuit layouts in hardware form (e.g., transistor-level implementations). In operation, logic synthesis tools scan one or more hand-drawn schematic diagrams to provide a set of equations that describe the circuit layout. The equations are then processed to create an efficient organization of the electronic logic gates for executing the equations. Typically, the output of a logic synthesizer is a netlist of circuit components and information needed to attain proper circuit implementation and operation.
Analysis of complete schematic diagrams of integrated circuit layouts to provide sets of boolean equations is, however, complex and time consuming for logic synthesis tools. Further, the schematic diagrams make evaluation of circuit control flow relatively difficult since the diagrams only represent hardwired connections of the circuit elements without any timing (e.q., control flow) information.
To reduce the complexity of automated circuit layout design, logic synthesis tools have been developed that receive a set of boolean equations as a direct input. Because these logic synthesis tools do not analyze schematic diagrams, they deprive circuit designers of the opportunity to work with and view schematic circuit layouts. Such synthesis tools do not permit visualization of both control flow and data flow in the circuit, and, instead, require circuit designers to work with relatively complex logical equations.